/*********************************************************************
*  ASTRIS - Remote JTAG probe
*
*  Astris Product ID definitions
*  File: astris_product_info.h
*
*********************************************************************
*
*  Copyright (C) 2020 Apple Inc. All rights reserved.
*
*  This document is the property of Apple Inc.
*  It is considered confidential and proprietary.
*
*  This document may not be reproduced or transmitted in any form,
*  in whole or in part, without the express written permission of
*  Apple Inc.
********************************************************************* */

/*
 * TODO: Implement product info as plist
 * <rdar://problem/62273549> Move Product Info to plist files in Astris API
 */

#ifndef astris_product_info_hpp
#define astris_product_info_hpp

#pragma once

#include "astris_api.h"

#define MAX_PMU_NAME_LEN  12
#define MAX_PROD_NAME_LEN 12

enum pmu_type_e {
    AGNES = 0,
    CALPE,
    BERKELIUM2,
    CALIFORNIUM,
    ATHENA,
    APPOLO,
    DENALI,
    BERYL,
    ATLAS,
    FERMIUM,
    IMOLA,
    AVUS,
    COTA,
    SERA,
    SIMETRA,
    SOCHI,
    MAVERICK,
    AINTREE,
    BAKU,
    FIREBIRD,
    STOWE,
    VALE,
    MIRABEAU,
    ESTORIL,
    CHAPEL,
    SPITFIRE,
    ABBEY,
    CLUB,
    SPECTER,
    MAX_PMUS
};

const char _pmu_name_str[MAX_PMUS][MAX_PMU_NAME_LEN] = {
    {"Agnes"      }, // D4422
    {"Calpe"      }, // D2449
    {"Berklium2"  }, // D2460
    {"Californium"}, // D2482
    {"Athena"     }, // D2483
    {"Appolo"     }, // D2537
    {"Denali"     }, // D2542
    {"Beryl"      },
    {"Atlas"      }, // D2652
    {"Fermium"    }, // D2720
    {"Imola"      }, // T500
    {"Avus"       }, // T504
    {"Cota"       }, // T5062
    {"Sera"       }, // T5064
    {"Simetra"    }, // T5064
    {"Sochi"      }, // T5068
    {"Maverick"   }, // T5078
    {"Aintree"    }, // T5076
    {"Baku"       }, // T5090
    {"Firebird"   },
    {"Stowe"      },
    {"Vale"       },
    {"Mirabeau"   }, // T5094
    {"Estoril"    }, // T5099
    {"Chapel"     }, // T5104
    {"Spitfire"   }, // T5100
    {"Abbey"      }, // T5110
    {"Club"       }, // T5108
    {"Specter"    }  // T5114
};

static constexpr astris_spmi_reg_addr_t SPMI_ADDR_UNKNOWN = 0;

// https://confluence.sd.apple.com/display/POWERTECH/Allocation+of+PMU+Scratchpad+Register+Space
const astris_spmi_reg_addr_t _pmu_socd_offset[MAX_PMUS] = {
    SPMI_ADDR_UNKNOWN, // AGNES
    0x400,             // CALPE
    SPMI_ADDR_UNKNOWN, // BERKELIUM2
    SPMI_ADDR_UNKNOWN, // CALIFORNIUM
    0xB00,             // ATHENA
    SPMI_ADDR_UNKNOWN, // APPOLO
    SPMI_ADDR_UNKNOWN, // DENALI
    SPMI_ADDR_UNKNOWN, // BERYL
    SPMI_ADDR_UNKNOWN, // ATLAS
    SPMI_ADDR_UNKNOWN, // FERMIUM
    SPMI_ADDR_UNKNOWN, // IMOLA
    SPMI_ADDR_UNKNOWN, // AVUS
    0xB00,             // COTA
    0xB00,             // SERA
    SPMI_ADDR_UNKNOWN, // SIMETRA
    0xB00,             // SOCHI
    0xB00,             // MAVERICK
    0xB00,             // AINTREE
    0x800,             // BAKU
    SPMI_ADDR_UNKNOWN, // FIREBIRD
    0xB00,             // STOWE
    SPMI_ADDR_UNKNOWN, // VALE
    0xB00,             // MIRABEAU
    0x4C8,             // ESTORIL (As of June 2023, still showing as "TBD"; Chris Zeitouny found this offset from AppleDialogSPMIPMU spew "SOCD: " when booting an N207)
    0xB00,             // CHAPEL
    SPMI_ADDR_UNKNOWN, // SPITFIRE
    0xB00,             // ABBEY (guess Jul 2022)
    0xB00,             // CLUB (guess Jul 2022)
    SPMI_ADDR_UNKNOWN, // SPECTER (leaf PMU without SOCD)
};

const astris_spmi_reg_addr_t _pmu_sram_base_addr[MAX_PMUS] = {
    0x8000,            // AGNES
    0x8000,            // CALPE
    0x7000,            // BERKELIUM2
    0x8000,            // CALIFORNIUM
    0x8000,            // ATHENA
    SPMI_ADDR_UNKNOWN, // APPOLO
    0x8000,            // DENALI
    SPMI_ADDR_UNKNOWN, // BERYL ??
    0x8000,            // ATLAS
    0x9000,            // FERMIUM
    0xA028,            // IMOLA
    0xA000,            // AVUS
    0xA000,            // COTA
    0xA000,            // SERA
    0xA000,            // SIMETRA
    0x9000,            // SOCHI
    0x8000,            // MAVERICK
    0xA000,            // AINTREE
    0x8000,            // BAKU
    SPMI_ADDR_UNKNOWN, // FIREBIRD
    0x8000,            // STOWE
    0xA000,            // VALE
    0x8000,            // MIRABEAU
    0x8000,            // ESTORIL
    0x8000,            // CHAPEL
    0xA000,            // SPITFIRE
    0x8000,            // ABBEY (guess)
    0x8000,            // CLUB (guess)
    0x8000,            // SPECTER (guess)
};

// Hard DFU support in PMU, from console/scripts/soc/socpmu.ax
const bool _pmu_hard_dfu[MAX_PMUS] = {
    true,  // AGNES
    true,  // CALPE
    false, // BERKELIUM2
    true,  // CALIFORNIUM
    true,  // ATHENA
    false, // APPOLO
    false, // DENALI
    true,  // BERYL
    true,  // ATLAS
    true,  // FERMIUM
    true,  // IMOLA
    true,  // AVUS
    true,  // COTA
    true,  // SERA
    true,  // SIMETRA
    true,  // SOCHI
    true,  // MAVERICK (expected)
    true,  // AINTREE
    true,  // BAKU
    false, // FIREBIRD
    true,  // STOWE
    true,  // VALE
    true,  // MIRABEAU
    true,  // ESTORIL
    true,  // CHAPEL
    true,  // SPITFIRE
    true,  // ABBEY
    true,  // CLUB
    true   // SPECTER
};

// Since PMU spmi dev address is 0xF for all PMUs for now,
// no need to create an array similar to _pmu_sram_base_addr
static const astris_spmi_dev_addr_t _pmu_spmi_addr = 0xF;

typedef struct {
    const char            *product_name;
    const char            *pmu_name;
    pmu_type_e             pmu;
    astris_spmi_dev_addr_t pmu_spmi_addr;
    astris_spmi_reg_addr_t pmu_sram_base_addr;
    astris_spmi_reg_addr_t pmu_socd_offset;
    AXdfu_type_t           dfu_mode;
    bool                   hard_dfu_support;
    uint32_t               board_id;
} prod_info_t;

#endif // astris_product_info_hpp
