/* ********************************************************************* * ASTRIS - Remote JTAG probe * * ARM DAP definitions File: armdap.h * ********************************************************************* * * Copyright (C) 2009-2017 Apple, Inc. All rights reserved. * * This document is the property of Apple Inc. * It is considered confidential and proprietary. * * This document may not be reproduced or transmitted in any form, * in whole or in part, without the express written permission of * Apple Inc. ********************************************************************* */ #ifndef _ARMDAP_H #define _ARMDAP_H #include "bitfields.h" /* ********************************************************************* * Constants ********************************************************************* */ /* Scan chain related stuff */ #define ARMDAP_CHLEN_BYTES 5 /* 4 data bytes + 3 more bits */ #define ARMDAP_CHLEN_BITS 35 /* Total scan chain length (bits) */ #define ARMDAP_IR_LEN 4 #define ARMDAP_IR_DPACC 0x50 /* b1010, bit-reversed, left justified */ #define ARMDAP_IR_APACC 0xD0 /* b1011, bit-reversed, left justified */ #define ARMDAP_IR_ABORT 0x10 /* b1000, bit-reversed, left justified */ #define ARMDAP_IR_BYPASS 0xF0 /* b1111, bit-reversed, left justified */ #define ARMDAP_IR_IDCODE 0x70 /* b1110, bit reversed, left justified */ /* APACC/DPACC register fields */ #define ARMDAP_READ 1 /* RnW: READ */ #define ARMDAP_WRITE 0 /* RnW: WRITE */ /* ACK field values */ #define ARMDAP_ACK_WRBUFF 8 /* Synthetic ACK: write buffer flushed (SWD only) */ #define ARMDAP_ACK_NOACK 7 /* ACK field: protocol error (SWD only) */ #define ARMDAP_ACK_FAULT 4 /* ACK field: FAULT (SWD only) */ #define ARMDAP_ACK_OKFAULT 2 /* ACK field: OK/Fault */ #define ARMDAP_ACK_WAIT 1 /* ACK field: wait (not ready) */ /* AP slot assignments */ #define ARMDAP_SEL_AHBAP 0 /* AHB-AP */ #define ARMDAP_SEL_APBAP 1 /* APB-AP */ #define ARMDAP_SEL_JTAGAP 2 /* JTAG-AP */ #define ARMDAP_SEL_DAPBUS 3 /* DAPBUS */ #define ARMDAP_SEL_AXIAP 4 /* AXI-AP */ /* ********************************************************************* * ABORT register ********************************************************************* */ #define M_APABORT_DAPABORT _MM_MAKEMASK1(0) #define M_APABORT_STCMPCLR _MM_MAKEMASK1(1) /* SW-DP only */ #define M_APABORT_STERRCLR _MM_MAKEMASK1(2) /* SW-DP only */ #define M_APABORT_WDERRCLR _MM_MAKEMASK1(3) /* SW-DP only */ #define M_APABORT_ORUNERRCLR _MM_MAKEMASK1(4) /* SW-DP only */ #define M_APABORT_STICKY (M_APABORT_STCMPCLR|M_APABORT_STERRCLR|M_APABORT_WDERRCLR|M_APABORT_ORUNERRCLR) /* ********************************************************************* * IDCODE register ********************************************************************* */ #define S_IDCODE_DESIGNER 1 #define M_IDCODE_DESIGNER _MM_MAKEMASK(11,S_IDCODE_DESIGNER) #define V_IDCODE_DESIGNER(v) _MM_MAKEVALUE((v),S_IDCODE_DESIGNER) #define G_IDCODE_DESIGNER(v) _MM_GETVALUE((v),S_IDCODE_DESIGNER,M_IDCODE_DESIGNER) #define S_IDCODE_PARTNO 12 #define M_IDCODE_PARTNO _MM_MAKEMASK(16,S_IDCODE_PARTNO) #define V_IDCODE_PARTNO(v) _MM_MAKEVALUE((v),S_IDCODE_PARTNO) #define G_IDCODE_PARTNO(v) _MM_GETVALUE((v),S_IDCODE_PARTNO,M_IDCODE_PARTNO) #define S_IDCODE_VERSION 28 #define M_IDCODE_VERSION _MM_MAKEMASK(4,S_IDCODE_VERSION) #define V_IDCODE_VERSION(v) _MM_MAKEVALUE((v),S_IDCODE_VERSION) #define G_IDCODE_VERSION(v) _MM_GETVALUE((v),S_IDCODE_VERSION,M_IDCODE_VERSION) /* ********************************************************************* * DP registers ********************************************************************* */ #define R_ARMDP_RSVD 0x00 /* Reserved (JTAG-DP) */ #define R_ARMDP_IDCODE 0x00 /* IDCODE register (SW-DP, RO) bank 0 */ #define R_ARMDP_ABORT 0x00 /* ABORT register (SW-DP, WO) */ #define R_ARMDP_DPIDR1 0x00 /* DPIDR1 DPv3 RO bank 1 */ #define R_ARMDP_BASEPTR0 0x00 /* BASEPTR0 DPv3 RO bank 2 */ #define R_ARMDP_BASEPTR1 0x00 /* BASEPTR1 DPv3 RO bank 3 */ #define R_ARMDP_CMDSTAT 0x04 /* Command/Status */ #define R_ARMDP_WCR 0x04 /* Wire Control Register (SW-DP only) */ #define R_ARMDP_TARGETID 0x04 /* TARGETID register when DPBANKSEL is 2 */ #define R_ARMDP_SELECT 0x08 /* Bank Select and AP select (WO) */ #define R_ARMDP_RESEND 0x08 /* RESEND register (SW-DP, RO) */ #define R_ARMDP_RDBUFF 0x0C /* RDBUFF (SW-DP, RO) */ #define R_ARMDP_TGTSEL 0x0C /* TGTSEL (SW-DP, WO) */ /* BASEPTR0 Register */ #define S_DPBASEPTR0_VALID 0 #define M_DPBASEPTR0_VALID _MM_MAKEMASK(1,S_DPBASEPTR0_VALID) #define V_DPBASEPTR0_VALID(v) _MM_MAKEVALUE((v),S_DPBASEPTR0_VALID) #define G_DPBASEPTR0_VALID(v) _MM_GETVALUE((v),S_DPBASEPTR0_VALID,M_DPBASEPTR0_VALID) #define S_DPBASEPTR0_PTR 12 #define M_DPBASEPTR0_PTR _MM_MAKEMASK(20,S_DPBASEPTR0_PTR) #define V_DPBASEPTR0_PTR(v) ((v) & M_DPBASEPTR0_PTR) #define G_DPBASEPTR0_PTR(v) ((v) & M_DPBASEPTR0_PTR) /* DPIDR1 Register */ #define S_DPIDR1_ASIZE 0 #define M_DPIDR1_ASIZE _MM_MAKEMASK(7,S_DPIDR1_ASIZE) #define V_DPIDR1_ASIZE(v) _MM_MAKEVALUE((v),S_DPIDR1_ASIZE) #define G_DPIDR1_ASIZE(v) _MM_GETVALUE((v),S_DPIDR1_ASIZE,M_DPIDR1_ASIZE) /* Command/Status Register */ #define M_DPCSR_ORUNDETECT _MM_MAKEMASK1(0) #define M_DPCSR_STICKYORUN _MM_MAKEMASK1(1) #define S_DPCSR_TRNMODE 2 #define M_DPCSR_TRNMODE _MM_MAKEMASK(2,S_DPCSR_TRNMODE) #define V_DPCSR_TRNMODE(v) _MM_MAKEVALUE((v),S_DPCSR_TRNMODE) #define G_DPCSR_TRNMODE(v) _MM_GETVALUE((v),S_DPCSR_TRNMODE,M_DPCSR_TRNMODE) #define K_DPCSR_TRNMODE_NORMAL 0 #define K_DPCSR_TRNMODE_PUSHEDVERIFY 1 #define K_DPCSR_TRNMODE_PUSHEDCOMPARE 2 #define K_DPCSR_TRNMODE_RESERVED 3 #define M_DPCSR_STICKYCMP _MM_MAKEMASK1(4) #define M_DPCSR_STICKYERR _MM_MAKEMASK1(5) #define M_DPCSR_READOK _MM_MAKEMASK1(6) /* SW-DP only */ #define M_DPCSR_WDATAERR _MM_MAKEMASK1(7) /* SW-DP only */ #define M_DPCSR_ERROR (M_DPCSR_STICKYORUN|M_DPCSR_STICKYCMP|M_DPCSR_STICKYERR|M_DPCSR_WDATAERR) #define S_DPCSR_MASKLANE 8 #define M_DPCSR_MASKLANE _MM_MAKEMASK(4,S_DPCSR_MASKLANE) #define V_DPCSR_MASKLANE(v) _MM_MAKEVALUE((v),S_DPCSR_MASKLANE) #define G_DPCSR_MASKLANE(v) _MM_GETVALUE((v),S_DPCSR_MASKLANE,M_DPCSR_MASKLANE) #define S_DPCSR_TRNCNT 12 #define M_DPCSR_TRNCNT _MM_MAKEMASK(12,S_DPCSR_TRNCNT) #define V_DPCSR_TRNCNT(v) _MM_MAKEVALUE((v),S_DPCSR_TRNCNT) #define G_DPCSR_TRNCNT(v) _MM_GETVALUE((v),S_DPCSR_TRNCNT,M_DPCSR_TRNCNT) #define M_DPCSR_CDBGRSTREQ _MM_MAKEMASK1(26) #define M_DPCSR_CDBGRSTACK _MM_MAKEMASK1(27) #define M_DPCSR_CDBGPWRUPREQ _MM_MAKEMASK1(28) #define M_DPCSR_CDBGPWRUPACK _MM_MAKEMASK1(29) #define M_DPCSR_CSYSPWRUPREQ _MM_MAKEMASK1(30) #define M_DPCSR_CSYSPWRUPACK _MM_MAKEMASK1(31) /* SELECT Register */ #define M_DPSEL_CTRLSEL _MM_MAKEMASK1(0) /* SW-DP only */ #define S_DPSEL_APBANKSEL 4 #define M_DPSEL_APBANKSEL _MM_MAKEMASK(4,S_DPSEL_APBANKSEL) #define V_DPSEL_APBANKSEL(v) _MM_MAKEVALUE((v),S_DPSEL_APBANKSEL) #define G_DPSEL_APBANKSEL(v) _MM_GETVALUE((v),S_DPSEL_APBANKSEL,M_DPSEL_APBANKSEL) #define S_DPSEL_APSEL 24 #define M_DPSEL_APSEL _MM_MAKEMASK(8,S_DPSEL_APSEL) #define V_DPSEL_APSEL(v) _MM_MAKEVALUE((v),S_DPSEL_APSEL) #define G_DPSEL_APSEL(v) _MM_GETVALUE((v),S_DPSEL_APSEL,M_DPSEL_APSEL) #define S_DPSEL_ADDR 4 #define M_DPSEL_ADDR _MM_MAKEMASK(28,S_DPSEL_ADDR ) #define V_DPSEL_ADDR(v) _MM_MAKEVALUE((v),S_DPSEL_ADDR ) #define G_DPSEL_ADDR(v) _MM_GETVALUE((v),S_DPSEL_ADDR ,M_DPSEL_ADDR ) #define M_REGADDR_BANKMASK 0xF0 /* Bits that go into the AP Bank Select */ #define S_REGADDR_BANKMASK 4 #define M_REGADDR_REGMASK 0x0C /* Bits that go into the A[3:2] field */ /* WCR register */ #define S_DPWCR_PRESCALER 0 #define M_DPWCR_PRESCALER _MM_MAKEMASK(3,S_DPWCR_PRESCALER) #define V_DPWCR_PRESCALER(v) _MM_MAKEVALUE((v),S_DPWCR_PRESCALER) #define G_DPWCR_PRESCALER(v) _MM_GETVALUE((v),S_DPWCR_PRESCALER,M_DPWCR_PRESCALER) #define S_DPWCR_WIREMODE 6 #define M_DPWCR_WIREMODE _MM_MAKEMASK(2,S_DPWCR_WIREMODE) #define V_DPWCR_WIREMODE(v) _MM_MAKEVALUE((v),S_DPWCR_WIREMODE) #define G_DPWCR_WIREMODE(v) _MM_GETVALUE((v),S_DPWCR_WIREMODE,M_DPWCR_WIREMODE) #define K_DPWCR_WIREMODE_ASYNC 0 /* hopefully not! */ #define K_DPWCR_WIREMODE_SYNC 1 /* hopefully */ #define S_DPWCR_TURNROUND 8 #define M_DPWCR_TURNROUND _MM_MAKEMASK(2,S_DPWCR_TURNROUND) #define V_DPWCR_TURNROUND(v) _MM_MAKEVALUE((v),S_DPWCR_TURNROUND) #define G_DPWCR_TURNROUND(v) _MM_GETVALUE((v),S_DPWCR_TURNROUND,M_DPWCR_TURNROUND) #define K_DPWCR_TURNROUND_1PERIOD 0 #define K_DPWCR_TURNROUND_2PERIOD 1 #define K_DPWCR_TURNROUND_3PERIOD 2 #define K_DPWCR_TURNROUND_4PERIOD 3 /* ********************************************************************* * Common AP registers ********************************************************************* */ /* * IDR register */ #define S_APIDR_REVISION 28 #define M_APIDR_REVISION _MM_MAKEMASK(4,S_APIDR_REVISION) #define V_APIDR_REVISION(v) _MM_MAKEVALUE((v),S_APIDR_REVISION) #define G_APIDR_REVISION(v) _MM_GETVALUE((v),S_APIDR_REVISION,M_APIDR_REVISION) #define S_APIDR_JEP106 17 #define M_APIDR_JEP106 _MM_MAKEMASK(11,S_APIDR_JEP106) #define V_APIDR_JEP106(v) _MM_MAKEVALUE((v),S_APIDR_JEP106) #define G_APIDR_JEP106(v) _MM_GETVALUE((v),S_APIDR_JEP106,M_APIDR_JEP106) #define K_APIDR_JEP106_ARMAP_LEGACY (0) #define K_APIDR_JEP106_ARMAP (0x3B | (0x04 << 7)) #define M_APIDR_CLASS_MEMAP _MM_MAKEMASK1(16) #define S_APIDR_VARIANT 4 #define M_APIDR_VARIANT _MM_MAKEMASK(4,S_APIDR_VARIANT) #define V_APIDR_VARIANT(v) _MM_MAKEVALUE((v),S_APIDR_VARIANT) #define G_APIDR_VARIANT(v) _MM_GETVALUE((v),S_APIDR_VARIANT,M_APIDR_VARIANT) #define S_APIDR_TYPE 0 #define M_APIDR_TYPE _MM_MAKEMASK(4,S_APIDR_TYPE) #define V_APIDR_TYPE(v) _MM_MAKEVALUE((v),S_APIDR_TYPE) #define G_APIDR_TYPE(v) _MM_GETVALUE((v),S_APIDR_TYPE,M_APIDR_TYPE) #define K_APIDR_TYPE_JTAG 0 /* AP is a JTAG_AP */ #define K_APIDR_TYPE_AHB 1 /* AP is an AMBA AHB Mem-AP */ #define K_APIDR_TYPE_APB 2 /* AP is an AMBA APB Mem-AP */ #define K_APIDR_TYPE_AXI 4 /* AP is an AMBA AXI Mem-AP */ #define K_APIDR_TYPE_AHB5 5 /* AP is an AMBA AHB5 Mem-AP */ #define K_APIDR_TYPE_AHB5_PROT 8 /* AP is an AMBA AHB5_PROT Mem-AP */ /* ********************************************************************* * Mem-AP Registers ********************************************************************* */ #define R_GENAP_IDR 0xFC /* Identification register (common) */ #define R_MEMAP_CSW 0x00 /* Control and Status Word */ #define R_MEMAP_TAR 0x04 /* Transfer address register */ #define R_MEMAP_TAR_HI 0x08 /* AXI-AP only, TAR[63:32] */ #define R_MEMAP_DRW 0x0C /* Data Read/Write register */ #define R_MEMAP_BD0 0x10 /* Banked data register 0 */ #define R_MEMAP_BD1 0x11 /* Banked data register 0 */ #define R_MEMAP_BD2 0x12 /* Banked data register 0 */ #define R_MEMAP_BD3 0x13 /* Banked data register 0 */ #define R_MEMAP_CFG 0xF4 /* Configuration register */ #define R_MEMAP_BASE 0xF8 /* Debug Base Address */ #define R_MEMAP_BASE_HI 0xF0 /* AXI-AP only, BASE[63:32] */ #define R_MEMAP_IDR R_GENAP_IDR /* Identification Register */ #define M_MEMAPCSW_DBGSWENABLE _MM_MAKEMASK1(31) #define M_MEMAPCSW_SPIDEN _MM_MAKEMASK1(23) #define S_MEMAPCSW_PROT 24 #define M_MEMAPCSW_PROT _MM_MAKEMASK(5,S_MEMAPCSW_PROT) #define V_MEMAPCSW_PROT(v) _MM_MAKEVALUE((v),S_MEMAPCSW_PROT) #define G_MEMAPCSW_PROT(v) _MM_GETVALUE((v),S_MEMAPCSW_PROT,M_MEMAPCSW_PROT) #define S_MEMAPCSW_DOMAIN 13 #define M_MEMAPCSW_DOMAIN _MM_MAKEMASK(2,S_MEMAPCSW_DOMAIN) #define V_MEMAPCSW_DOMAIN(v) _MM_MAKEVALUE((v),S_MEMAPCSW_DOMAIN) #define G_MEMAPCSW_DOMAIN(v) _MM_GETVALUE((v),S_MEMAPCSW_DOMAIN,M_MEMAPCSW_DOMAIN) #define K_MEMAPCSW_DOMAIN_NS 0 /* b00 = Non Shareable */ #define K_MEMAPCSW_DOMAIN_SIN 1 /* b01 = Shareable, inner domain includes additional masters */ #define K_MEMAPCSW_DOMAIN_SOUT 2 /* b10 = Shareable, outer domain, also includes inner/additional masters */ #define K_MEMAPCSW_DOMAIN_SALL 3 /* b11 = Shareable, System domain, all masters included */ #define M_MEMAPCSW_TRINPROG _MM_MAKEMASK1(7) #define M_MEMAPCSW_DEVICEEN _MM_MAKEMASK1(6) #define S_MEMAPCSW_MODE 8 #define M_MEMAPCSW_MODE _MM_MAKEMASK(4,S_MEMAPCSW_MODE) #define V_MEMAPCSW_MODE(v) _MM_MAKEVALUE((v),S_MEMAPCSW_MODE) #define G_MEMAPCSW_MODE(v) _MM_GETVALUE((v),S_MEMAPCSW_MODE,M_MEMAPCSW_MODE) #define K_MEMAPCSW_MODE 0 /* only supported value */ #define S_MEMAPCSW_ADDRINC 4 #define M_MEMAPCSW_ADDRINC _MM_MAKEMASK(2,S_MEMAPCSW_ADDRINC) #define V_MEMAPCSW_ADDRINC(v) _MM_MAKEVALUE((v),S_MEMAPCSW_ADDRINC) #define G_MEMAPCSW_ADDRINC(v) _MM_GETVALUE((v),S_MEMAPCSW_ADDRINC,M_MEMAPCSW_ADDRINC) #define K_MEMAPCSW_ADDRINC_OFF 0 #define K_MEMAPCSW_ADDRINC_INCSINGLE 1 #define K_MEMAPCSW_ADDRINC_INCPACKED 2 #define K_MEMAPCSW_ADDRINC_RESERVED 3 #define S_MEMAPCSW_SIZE 0 #define M_MEMAPCSW_SIZE _MM_MAKEMASK(3,S_MEMAPCSW_SIZE) #define V_MEMAPCSW_SIZE(v) _MM_MAKEVALUE((v),S_MEMAPCSW_SIZE) #define G_MEMAPCSW_SIZE(v) _MM_GETVALUE((v),S_MEMAPCSW_SIZE,M_MEMAPCSW_SIZE) #define K_MEMAPCSW_SIZE_8BIT 0 #define K_MEMAPCSW_SIZE_16BIT 1 #define K_MEMAPCSW_SIZE_32BIT 2 /* only required supported value */ #define K_MEMAPCSW_SIZE_64BIT 3 #define K_MEMAPCSW_SIZE_128BIT 4 #define K_MEMAPCSW_SIZE_256BIT 5 #define M_MEMAPCFG_BIGENDIAN _MM_MAKEMASK1(0) #define M_MEMAPBASE_ADDR 0xFFFFF000 #define M_MEMAPBASE_V5FORMAT _MM_MAKEMASK1(1) #define M_MEMAPBASE_PRESENT _MM_MAKEMASK1(0) #define K_MEMAPBASE_NOTPRESENT 0xFFFFFFFF // This basically includes ADDRINC + SIZE #define M_MEMAPCSW_XACT_CFG _MM_MAKEMASK(6, 0) #define K_AP_MEMAP_ADIV6_OFFSET 0xD00 /* ADIv6 Offset */ /* ********************************************************************* * CoreSight component registers ********************************************************************* */ #define R_CS_DEVICE_CONIFG 0xFC8 #define R_CS_DEVICE_TYPE 0xFCC #define R_CS_COMPONENT_ID0 0xFF0 #define R_CS_COMPONENT_ID1 0xFF4 #define R_CS_COMPONENT_ID2 0xFF8 #define R_CS_COMPONENT_ID3 0xFFC #define R_CS_PERIPHERAL_ID0 0xFE0 #define R_CS_PERIPHERAL_ID1 0xFE4 #define R_CS_PERIPHERAL_ID2 0xFE8 #define R_CS_PERIPHERAL_ID3 0xFEC #define R_CS_PERIPHERAL_ID4 0xFD0 #define R_CS_PERIPHERAL_ID5 0xFD4 #define R_CS_PERIPHERAL_ID6 0xFD8 #define R_CS_PERIPHERAL_ID7 0xFDC #define K_CS_DEVTYPE_MAJOR_LOGIC 5 #define K_CS_DEVTYPE_MAJOR_TRACESOURCE 3 #define K_CS_DEVTYPE_MAJOR_CROSSTRIGGER 4 #define K_CS_DEVTYPE_MAJOR_FUNNEL 2 #define K_CS_DEVTYPE_MAJOR_TRACESINK 1 #define K_CS_DEVTYPE_SUB_PROCESSOR 1 #define K_CS_DEVICE_TYPE_CPU 0x15 #define K_CS_DEVICE_TYPE_ETB 0x21 /* subtype 2? */ #define K_CS_DEVICE_TYPE_ITM 0x43 #define K_CS_DEVICE_TYPE_CTI 0x14 #define K_CS_DEVICE_TYPE_TPIU 0x11 #define K_CS_DEVICE_TYPE_CSTF 0X12 #define K_CS_DEVICE_TYPE_ETM 0X13 #define K_CS_DEVICE_TYPE_PMU 0X16 #define S_CS_DEVICE_TYPE_MAJOR 0 #define M_CS_DEVICE_TYPE_MAJOR _MM_MAKEMASK(4,S_CS_DEVICE_TYPE_MAJOR) #define V_CS_DEVICE_TYPE_MAJOR(v) _MM_MAKEVALUE((v),S_CS_DEVICE_TYPE_MAJOR) #define G_CS_DEVICE_TYPE_MAJOR(v) _MM_GETVALUE((v),S_CS_DEVICE_TYPE_MAJOR,M_CS_DEVICE_TYPE_MAJOR) #define S_CS_DEVICE_TYPE_SUB 4 #define M_CS_DEVICE_TYPE_SUB _MM_MAKEMASK(4,S_CS_DEVICE_TYPE_SUB) #define V_CS_DEVICE_TYPE_SUB(v) _MM_MAKEVALUE((v),S_CS_DEVICE_TYPE_SUB) #define G_CS_DEVICE_TYPE_SUB(v) _MM_GETVALUE((v),S_CS_DEVICE_TYPE_SUB,M_CS_DEVICE_TYPE_SUB) #define S_COMPONENT_CLASS 4 #define M_COMPONENT_CLASS _MM_MAKEMASK(4,S_COMPONENT_CLASS) #define V_COMPONENT_CLASS(v) _MM_MAKEVALUE((v),S_COMPONENT_CLASS) #define G_COMPONENT_CLASS(v) _MM_GETVALUE((v),S_COMPONENT_CLASS,M_COMPONENT_CLASS) #define K_COMPONENT_CLASS_GENERICVERIF 0x0 #define K_COMPONENT_CLASS_ROMTABLE 0x1 #define K_COMPONENT_CLASS_DBGCOMPONENT 0x9 #define K_COMPONENT_CLASS_PERIPHTESTBLK 0xB #define K_COMPONENT_CLASS_OPTIMODE 0xD #define K_COMPONENT_CLASS_GENERICIP 0xE #define K_COMPONENT_CLASS_PRIMECELL 0xF #define MAKE_JDEC_PARTNUMBER_ID(cc,c,part) ((cc << 20) | (1<<19) | (c << 12) | part) #define MAKE_JDEC_PARTNUMBER_ID_FROM_PIDS(p0,p1,p2,p4) (((p4 & 0xF) << 20) | ((p2 & 0xF) << 16) | (p1 << 8) | p0) #define ARM_JEP106_CODE 0x3B #define ARM_JEP106_CCODE 0x04 #define APPLE_JEP106_CODE 0x48 #define APPLE_JEP106_CCODE 0x00 /* ********************************************************************* * ROM Table offsets ********************************************************************* */ #define R_ROMTBL_ENTRIES 0 #define R_ROMTBL_MEMTYPE 0xFCC #define R_ROMTBL_PERIPHERAL_ID 0xFD0 #define R_ROMTBL_COMPONENT_ID 0xFF0 #define M_ROMTBL_MEMTYPE_SYSMEMPRESENT _MM_MAKEMASK1(0) #define M_ROMTBL_ENTRY_32BIT _MM_MAKEMASK1(1) #define M_ROMTBL_ENTRY_PRESENT _MM_MAKEMASK1(0) #define M_ROMTBL_ENTRY_ADDRESS 0xFFFFF000 /* ********************************************************************* * JTAG-AP stuff ********************************************************************* */ #define R_JTAGAP_CSW 0x00 /* Command / Status */ #define R_JTAGAP_PSEL 0x04 /* Port Select */ #define R_JTAGAP_PSTA 0x08 /* Port Status */ #define R_JTAGAP_BXFIFO1 0x10 /* Byte FIFO 1 */ #define R_JTAGAP_BXFIFO2 0x14 /* Byte FIFO 2 */ #define R_JTAGAP_BXFIFO3 0x18 /* Byte FIFO 3 */ #define R_JTAGAP_BXFIFO4 0x1C /* Byte FIFO 4 */ #define R_JTAGAP_IDR 0xFC /* Identification */ #define M_JTAGAPCSW_SRST_OUT _MM_MAKEMASK1(0) #define M_JTAGAPCSW_TRST_OUT _MM_MAKEMASK1(1) #define M_JTAGAPCSW_SRSTCONN _MM_MAKEMASK1(2) #define M_JTAGAPCSW_PORTCONN _MM_MAKEMASK1(3) #define S_JTAGAPCSW_RFIFOCNT 24 #define M_JTAGAPCSW_RFIFOCNT _MM_MAKEMASK(3,S_JTAGAPCSW_RFIFOCNT) #define V_JTAGAPCSW_RFIFOCNT(v) _MM_MAKEVALUE((v),S_JTAGAPCSW_RFIFOCNT) #define G_JTAGAPCSW_RFIFOCNT(v) _MM_GETVALUE((v),S_JTAGAPCSW_RFIFOCNT,M_JTAGAPCSW_RFIFOCNT) #define S_JTAGAPCSW_WFIFOCNT 28 #define M_JTAGAPCSW_WFIFOCNT _MM_MAKEMASK(3,S_JTAGAPCSW_WFIFOCNT) #define V_JTAGAPCSW_WFIFOCNT(v) _MM_MAKEVALUE((v),S_JTAGAPCSW_WFIFOCNT) #define G_JTAGAPCSW_WFIFOCNT(v) _MM_GETVALUE((v),S_JTAGAPCSW_WFIFOCNT,M_JTAGAPCSW_WFIFOCNT) #define M_JTAGAPCSW_SERACTV _MM_MAKEMASK1(31) #define M_JTAGAPPSEL_PSELX(x) _MM_MAKEMASK1(x) #define M_JTAGAPPSTA_PSTAX(x) _MM_MAKEMASK1(x) #define M_JTAGAP_TDITDO_OP 0x80 /* for TDI_TDO packet */ #define M_JTAGAP_TMS_OP 0x00 /* for TMS packets */ #define K_JTAGAP_MAXPORTS 8 /* * TDI_TDO opcode byte */ #define M_JTAGAP_TDITDO_UTDI 0x01 #define M_JTAGAP_TDITDO_TDI 0x02 #define M_JTAGAP_TDITDO_RTDO 0x04 #define M_JTAGAP_TDITDO_TMS 0x08 /* XXX additional stuff should go here to describe JTAG packets */ #endif